21 lines
406 B
Systemverilog
21 lines
406 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface wb_ifc;
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logic clk;
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wire rst;
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tri0 cyc;
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clocking mck @(posedge clk);
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input rst;
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output cyc;
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endclocking
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endinterface
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module t;
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wb_ifc wb_ma ();
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initial $finish;
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endmodule
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