22 lines
436 B
Systemverilog
22 lines
436 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Geza Lore
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [2:0] cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 3'd1;
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// Exit via abort to make sure trace is flushed
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if (&cyc) $stop;
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end
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endmodule
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