21 lines
390 B
Systemverilog
21 lines
390 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg b = 0, c = 1;
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always @(posedge clk) begin
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fork
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b <= c;
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c <= b;
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join
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end
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endmodule
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