41 lines
1.0 KiB
Systemverilog
41 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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parameter P = 4'h5;
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typedef struct { // Must be unpacked -- existing error check
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// Update ctor_var_reset to check instead of making a constructor
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bit [3:0] m_lo = P;
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bit [93:0] m_mid = '1; // Wide
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bit [3:0] m_hi;
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} s_t;
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s_t s;
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initial begin
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$display("%p", s);
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`checkh(s.m_lo, 4'h5);
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`checkh(s.m_mid, ~94'h0);
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`checkh(s.m_hi, 4'h0);
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s.m_mid = 94'ha;
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s.m_hi = 4'hb;
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$display("%p", s);
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`checkh(s.m_lo, 4'h5);
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`checkh(s.m_mid, 94'ha);
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`checkh(s.m_hi, 4'hb);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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