26 lines
630 B
Systemverilog
26 lines
630 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t ();
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for (genvar g = 0; g < 2; ++g) begin : genfor
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typedef struct packed {
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logic [31:0] val1;
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logic [31:0] val2;
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} struct_t;
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struct_t forvar;
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initial begin
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forvar.val1 = 1;
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forvar.val2 = 2;
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if (forvar.val1 != 1) $stop;
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if (forvar.val2 != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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