24 lines
566 B
Systemverilog
24 lines
566 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t;
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initial begin
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randsequence()
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a: {
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randsequence()
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b: {};
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endsequence
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};
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endsequence
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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