19 lines
434 B
Systemverilog
19 lines
434 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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class ex;
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randc struct {logic m_x;} s; // <--- Bad: randc illegal on unpacked struct
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randc struct packed {logic m_x;} p_s; // Ok
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endclass : ex
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module foo;
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initial begin
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ex e;
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void'(e.randomize());
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end
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endmodule
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