29 lines
618 B
Systemverilog
29 lines
618 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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typedef struct {int x;} struct_t;
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class ConstrClass;
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struct_t obj;
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rand int rand_int;
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constraint addr_c {rand_int == obj.x;}
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endclass
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module t;
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ConstrClass o;
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initial begin
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o = new;
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o.obj.x = 42;
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if (o.randomize() == 0) begin
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$display("Randomization failed");
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$stop;
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end
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else if (o.obj.x != o.rand_int) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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