23 lines
546 B
Systemverilog
23 lines
546 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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package uvm_pkg;
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class uvm_sequence_item;
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endclass
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endpackage
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package tb_cpu_pkg;
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import uvm_pkg::*;
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class tb_cpu_seq_item extends uvm_sequence_item;
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function void pre_randomize();
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super.pre_randomize();
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endfunction
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function void post_randomize();
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super.post_randomize();
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endfunction
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endclass
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endpackage
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