27 lines
614 B
Systemverilog
27 lines
614 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t;
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process job;
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initial begin
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automatic process p1 = process::self();
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fork
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begin
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wait (p1.status() != process::RUNNING);
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$write("job started\n");
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job = process::self();
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end
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join_none
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wait (job);
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$write("all jobs started\n");
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job.await();
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$write("all jobs finished\n");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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