13 lines
389 B
Systemverilog
13 lines
389 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test for issue where assignment pattern with XOR caused segfault
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module t;
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typedef struct {logic bit_field;} status_t;
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status_t status_reg = '{bit_field: 1'b0} ^ 1'b0;
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endmodule
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