14 lines
346 B
Systemverilog
14 lines
346 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2019 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t #(parameter P, parameter type T);
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generate
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var j;
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for (j=0; P; j++)
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initial begin end
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endgenerate
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endmodule
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