17 lines
321 B
Systemverilog
17 lines
321 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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package Foo;
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endpackage
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package Bar;
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static int baz;
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endpackage
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module t;
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int baz = Foo::Bar::baz;
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endmodule
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