16 lines
372 B
Systemverilog
16 lines
372 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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for (genvar k = 0; k < 1; k++) begin : gen_empty
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// empty
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end
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initial
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for (int i = 0; i < 1; i++) begin : gen_i
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// empty
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end
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endmodule
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