159 lines
2.6 KiB
Systemverilog
159 lines
2.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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// direct task call
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module mod0 #(
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) (
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input logic sel,
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output logic val
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);
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logic l0;
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task do_stuff();
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l0 = 'b1;
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endtask
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always_comb begin
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l0 = 'b0;
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if (sel) begin
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do_stuff();
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end
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end
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assign val = l0;
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endmodule
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// nested task call chain
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module mod1 #(
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) (
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input logic sel,
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output logic val
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);
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logic l0;
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task do_inner();
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l0 = 'b1;
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endtask
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task do_outer();
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do_inner();
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endtask
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always_comb begin
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l0 = 'b0;
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if (sel) do_outer();
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end
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assign val = l0;
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endmodule
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// task writes through an output arguement
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module mod2 #(
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) (
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input logic sel,
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output logic val
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);
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logic l0;
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task automatic do_stuff(output logic q);
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q = 1'b1;
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endtask
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always_comb begin
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l0 = 1'b0;
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if (sel) do_stuff(l0);
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end
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assign val = l0;
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endmodule
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// function call that writes
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module mod3 #(
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) (
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input logic sel,
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output logic val
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);
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logic l0;
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function automatic void do_func();
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l0 = 1'b1;
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endfunction
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always_comb begin
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l0 = 1'b0;
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if (sel) do_func();
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end
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assign val = l0;
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endmodule
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// two tasks set0/set1
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module mod4 #(
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) (
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input logic sel,
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output logic val
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);
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logic l0;
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task automatic set1();
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l0 = 1'b1;
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endtask
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task automatic set0();
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l0 = 1'b0;
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endtask
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always_comb begin
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set0();
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if (sel) begin
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set1();
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end
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end
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assign val = l0;
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endmodule
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module m_tb;
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logic sel;
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logic v0, v1, v2, v3, v4;
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mod0 u0 (
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.sel(sel),
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.val(v0)
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);
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mod1 u1 (
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.sel(sel),
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.val(v1)
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);
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mod2 u2 (
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.sel(sel),
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.val(v2)
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);
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mod3 u3 (
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.sel(sel),
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.val(v3)
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);
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mod4 u4 (
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.sel(sel),
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.val(v4)
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);
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initial begin
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#1;
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sel = 0;
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`checkd(v0, 0);
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`checkd(v1, 0);
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`checkd(v2, 0);
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`checkd(v3, 0);
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`checkd(v4, 0);
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#1;
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sel = 1;
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`checkd(v0, 1);
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`checkd(v1, 1);
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`checkd(v2, 1);
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`checkd(v3, 1);
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`checkd(v4, 1);
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#1;
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sel = 0;
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`checkd(v0, 0);
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`checkd(v1, 0);
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`checkd(v2, 0);
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`checkd(v3, 0);
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`checkd(v4, 0);
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#1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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