17 lines
435 B
Systemverilog
17 lines
435 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This test verifies that a top-module can be specified which
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// is instantiated beneath another module in the compiled source
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// code.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t_mod_topmodule__underunder;
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initial $finish;
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endmodule
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module faketop;
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endmodule
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