41 lines
869 B
Systemverilog
41 lines
869 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008 Lane Brooks
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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o3, o34, o345,
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// Inputs
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i3, i34, i345
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);
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input [15:0] i3;
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output wire [15:0] o3;
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input [15:0] i34 [3:0];
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output wire [15:0] o34 [3:0];
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input [15:0] i345 [3:0][4:0];
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output wire [15:0] o345 [3:0][4:0];
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sub sub (.*);
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endmodule
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module sub (/*AUTOARG*/
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// Outputs
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o3, o34, o345,
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// Inputs
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i3, i34, i345
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);
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input [15:0] i3;
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output wire [15:0] o3;
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input [15:0] i34 [3:0];
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output wire [15:0] o34 [3:0];
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input [15:0] i345 [3:0][4:0];
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output wire [15:0] o345 [3:0][4:0];
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assign o3 = i3;
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assign o34 = i34;
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assign o345 = i345;
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endmodule
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