18 lines
342 B
Systemverilog
18 lines
342 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2010 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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sub sub ();
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defparam sub.P = 2;
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endmodule
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module sub;
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parameter P = 6;
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if (P != 0) ; // Prevent unused
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endmodule
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