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// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2019 Todd Strader
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// SPDX-License-Identifier: CC0-1.0
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module secret_impl;
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initial begin
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#10;
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$stop;
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end
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endmodule
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