19 lines
341 B
Systemverilog
19 lines
341 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface Ifc;
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endinterface
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module Sub;
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Ifc a();
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endmodule
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module t;
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Sub sub();
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// Issue #5649
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wire wbad = sub.a;
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endmodule
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