21 lines
384 B
Systemverilog
21 lines
384 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface stream_ifc #(
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) (
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input logic clk_i
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);
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endinterface
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package pkg;
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class stream_driver #();
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virtual stream_ifc stream;
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endclass
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endpackage
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module t;
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endmodule
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