23 lines
472 B
Systemverilog
23 lines
472 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2010 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface ifc;
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logic [3:0] value;
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logic reset;
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modport counter_mp (input reset, output value);
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modport core_mp (output reset, input value);
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endinterface
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module t
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(// Inputs
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input clk,
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ifc.counter_mp c_data
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);
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integer cyc=1;
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endmodule
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