138 lines
4.0 KiB
Systemverilog
138 lines
4.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Leela Pakanati
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// SPDX-License-Identifier: CC0-1.0
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// Test for Issue #5941 and #2656: Modport interface field access via hierarchy
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// Tests:
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// - Single-level and deep hierarchical access
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// - Multiple interface instances (same modport type, different data)
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// - Interface arrays
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interface bus_if (input logic clk);
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logic [7:0] data;
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modport slave (output data, input clk);
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endinterface
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// l1 module with the actual logic
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module l1_mod (bus_if.slave bus);
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always_ff @(posedge bus.clk)
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bus.data <= 8'h5A;
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endmodule
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// l0 module wrapping l1 module
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module l0_mod (bus_if.slave bus);
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l1_mod l1_inst (bus);
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endmodule
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// Modules for testing multiple instances with same modport
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module mod_aa (bus_if.slave bus);
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assign bus.data = 8'hAA;
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endmodule
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module mod_bb (bus_if.slave bus);
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assign bus.data = 8'hBB;
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endmodule
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// Module for testing interface arrays
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module array_mod (bus_if.slave bus[2]);
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always_ff @(posedge bus[0].clk) begin
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bus[0].data <= 8'hA0;
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bus[1].data <= 8'hA1;
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end
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endmodule
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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// Deep hierarchy test
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bus_if bus (clk);
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l0_mod l0_inst (bus);
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// Multiple instances test
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bus_if bus_a (clk);
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bus_if bus_b (clk);
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mod_aa inst_aa (bus_a);
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mod_bb inst_bb (bus_b);
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// Array test
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bus_if bus_arr[2] (clk);
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array_mod array_inst (bus_arr);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 5) begin
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// === Deep hierarchy tests ===
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$display("bus.data = %h (direct)", bus.data);
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$display("l0_inst.bus.data = %h (single-level)", l0_inst.bus.data);
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$display("l0_inst.l1_inst.bus.data = %h (deep)", l0_inst.l1_inst.bus.data);
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if (bus.data !== 8'h5A) begin
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$display("%%Error: bus.data = %h, expected 5A", bus.data);
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$stop;
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end
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if (l0_inst.bus.data !== 8'h5A) begin
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$display("%%Error: l0_inst.bus.data = %h, expected 5A", l0_inst.bus.data);
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$stop;
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end
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if (l0_inst.l1_inst.bus.data !== 8'h5A) begin
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$display("%%Error: l0_inst.l1_inst.bus.data = %h, expected 5A", l0_inst.l1_inst.bus.data);
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$stop;
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end
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if (l0_inst.bus.clk !== clk) begin
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$display("%%Error: l0_inst.bus.clk mismatch");
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$stop;
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end
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if (l0_inst.l1_inst.bus.clk !== clk) begin
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$display("%%Error: l0_inst.l1_inst.bus.clk mismatch");
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$stop;
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end
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// === Multiple instances tests (bug #2656) ===
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$display("inst_aa.bus.data = %h", inst_aa.bus.data);
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$display("inst_bb.bus.data = %h", inst_bb.bus.data);
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if (inst_aa.bus.data !== 8'hAA) begin
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$display("%%Error: inst_aa.bus.data = %h, expected AA", inst_aa.bus.data);
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$stop;
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end
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if (inst_bb.bus.data !== 8'hBB) begin
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$display("%%Error: inst_bb.bus.data = %h, expected BB", inst_bb.bus.data);
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$stop;
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end
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// === Interface array tests (bug #2656) ===
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$display("bus_arr[0].data = %h (direct)", bus_arr[0].data);
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$display("bus_arr[1].data = %h (direct)", bus_arr[1].data);
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$display("array_inst.bus[0].data = %h (hierarchical)", array_inst.bus[0].data);
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$display("array_inst.bus[1].data = %h (hierarchical)", array_inst.bus[1].data);
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if (bus_arr[0].data !== 8'hA0) begin
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$display("%%Error: bus_arr[0].data = %h, expected A0", bus_arr[0].data);
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$stop;
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end
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if (bus_arr[1].data !== 8'hA1) begin
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$display("%%Error: bus_arr[1].data = %h, expected A1", bus_arr[1].data);
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$stop;
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end
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if (array_inst.bus[0].data !== 8'hA0) begin
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$display("%%Error: array_inst.bus[0].data = %h, expected A0", array_inst.bus[0].data);
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$stop;
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end
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if (array_inst.bus[1].data !== 8'hA1) begin
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$display("%%Error: array_inst.bus[1].data = %h, expected A1", array_inst.bus[1].data);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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