72 lines
1.8 KiB
Systemverilog
72 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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interface my_if #(parameter WIDTH = 1);
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logic [WIDTH-1:0] sig_a, sig_b, sig_c, sig_d;
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logic [WIDTH-1:0] sig_e, sig_f;
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// Multiple expressions same direction
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logic [WIDTH-1:0] m1, m2, m3;
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modport mp1(input .a(sig_a), output .b(sig_b));
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modport mp2(input .a(sig_c), output .b(sig_d));
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// Mixed regular and expression items
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modport mp3(input sig_e, output .f(sig_f));
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// Multiple expressions with same direction
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modport mp4(input .in1(m1), input .in2(m2), output .out(m3));
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endinterface
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module mod1 (
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my_if.mp1 i
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);
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assign i.b = i.a;
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endmodule
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module mod2 (
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my_if.mp2 i
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);
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assign i.b = i.a;
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endmodule
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module mod3 (
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my_if.mp3 i
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);
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assign i.f = i.sig_e; // sig_e is regular, f is expression
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endmodule
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module mod4 (
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my_if.mp4 i
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);
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assign i.out = i.in1 ^ i.in2;
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endmodule
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module top ();
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my_if #(.WIDTH(8)) myIf ();
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assign myIf.sig_a = 8'h42, myIf.sig_c = 8'hAB;
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assign myIf.sig_e = 8'hCD;
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assign myIf.m1 = 8'hF0, myIf.m2 = 8'h0F;
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mod1 mod1i (myIf.mp1);
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mod2 mod2i (myIf.mp2);
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mod3 mod3i (myIf.mp3);
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mod4 mod4i (myIf.mp4);
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initial begin
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#1;
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`checkh(myIf.sig_b, 8'h42); // mp1: b = a
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`checkh(myIf.sig_d, 8'hAB); // mp2: b = a
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`checkh(myIf.sig_f, 8'hCD); // mp3: f = sig_e
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`checkh(myIf.m3, 8'hFF); // mp4: out = in1 ^ in2
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#1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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