18 lines
426 B
Systemverilog
18 lines
426 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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interconnect a;
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assign a = 1; // Bad IEEE 6.6.8 - shall not be used in continuous assignment
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initial begin
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a = 2; // Bad IEEE 6.6.8 - shall not be used in procedural assignment
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end
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endmodule
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