19 lines
492 B
Systemverilog
19 lines
492 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire ok = 1'b0;
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// verilator lint_off UNDRIVEN
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wire nc;
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// verilator lint_on UNDRIVEN
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sub sub (ok, , nc);
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endmodule
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module sub (input ok, input none, input nc, input missing);
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initial if (ok && none && nc && missing) begin end // No unused warning
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endmodule
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