14 lines
322 B
Systemverilog
14 lines
322 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2019 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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int a = -12'd1;
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int b = 65536'd1;
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int c = 1231232312312312'd1;
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int e = 12'1;
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int f = 12'0;
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int g = 12'z;
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int h = 12'x;
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