23 lines
436 B
Systemverilog
23 lines
436 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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function logic get_x(ref logic x);
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return x;
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endfunction
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endclass
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module t;
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logic [10:0] a;
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logic b;
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Cls cls;
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initial begin
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cls = new;
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b = cls.get_x(a[1]);
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$stop;
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end
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endmodule
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