22 lines
498 B
Systemverilog
22 lines
498 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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task main;
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integer varintask;
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varintask = 0;
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while (varintask < 4) begin
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varintask = varintask + 1;
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end
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if (varintask != 4) $stop;
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endtask
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initial begin
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main;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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