42 lines
1.1 KiB
Systemverilog
42 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Test for IEEE 1800-2023 6.22.2 - valid array assignments with matching state types
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// 2-state arrays - assignment should work
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bit [7:0] arr_2state_a[3:0];
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bit [7:0] arr_2state_b[3:0];
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// 4-state arrays - assignment should work
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logic [7:0] arr_4state_a[3:0];
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logic [7:0] arr_4state_b[3:0];
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initial begin
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// Initialize
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arr_2state_a[0] = 8'h10;
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arr_2state_a[1] = 8'h20;
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arr_2state_a[2] = 8'h30;
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arr_2state_a[3] = 8'h40;
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arr_4state_a[0] = 8'hA0;
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arr_4state_a[1] = 8'hB0;
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arr_4state_a[2] = 8'hC0;
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arr_4state_a[3] = 8'hD0;
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// Valid assignments: same state types
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arr_2state_b = arr_2state_a; // 2-state to 2-state: OK
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arr_4state_b = arr_4state_a; // 4-state to 4-state: OK
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// Verify
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if (arr_2state_b[0] !== 8'h10) $stop;
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if (arr_2state_b[3] !== 8'h40) $stop;
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if (arr_4state_b[0] !== 8'hA0) $stop;
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if (arr_4state_b[3] !== 8'hD0) $stop;
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$write("*-* All Coverage *-*\n");
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$finish;
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end
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endmodule
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