24 lines
473 B
Systemverilog
24 lines
473 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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class bar;
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task foo(logic r);
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int a, b;
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if (r) return;
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fork a = #1 b; join_none
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endtask
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endclass
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module t;
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bar b = new;
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initial begin
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b.foo(0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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