60 lines
1.5 KiB
Systemverilog
60 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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task do_something(int arg_v);
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int dynscope_var;
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int x;
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if (dynscope_var != 0) $stop;
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dynscope_var = 10;
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if (dynscope_var != 10) $stop;
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fork
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#10 begin
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x = 0;
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// Test capturing a variable that needs to be modified
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if (dynscope_var != 10) $stop;
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$display("Incremented dynscope_var: %0d", ++dynscope_var);
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if (dynscope_var != 11) $stop;
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// Check nested access
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fork
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#10 begin
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$display("Incremented x: %0d", ++x);
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$display("Incremented dynscope_var: %0d", ++dynscope_var);
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if (dynscope_var != 12) $stop;
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end
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join_none
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end
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#10 begin
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// Same as the first check, but with an argument
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// (so it needs to be copied to the dynamic scope instead of being moved there)
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if (arg_v != 1) $stop;
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$display("Incremented arg_v: %0d", ++arg_v);
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if (arg_v != 2) $stop;
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end
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join_none
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// Check if regular access to arg_v has been substituted with access to its copy from
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// a dynamic scope
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$display("Incremented arg_v: %0d", ++arg_v);
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if (arg_v != 1) $stop;
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endtask
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endclass
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module t;
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initial begin
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Foo foo;
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foo = new;
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foo.do_something(0);
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#99 begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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