30 lines
652 B
Systemverilog
30 lines
652 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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typedef struct {int x[9][9];} Foo;
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class Bar;
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Foo foo;
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function automatic void test();
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foreach(this.foo.x[i])
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foreach(this.foo.x[i][j])
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this.foo.x[i][j] = i * j;
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for (int i = 0; i < 9; i++)
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for (int j = 0; j < 9; j++)
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if (this.foo.x[i][j] != i * j) $stop;
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endfunction
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endclass
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module t;
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initial begin
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automatic Bar b = new;
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b.test;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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