39 lines
577 B
Systemverilog
39 lines
577 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input x,
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input y,
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output z
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);
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logic t2 /* verilator public */;
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logic t3;
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sub u_sub (
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x,
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y,
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t3
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);
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assign t2 = t3 | x;
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assign z = t2;
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endmodule
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module sub (
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input a /* verilator forceable */ /* verilator public_flat */,
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input b,
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output c
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);
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logic t1;
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assign t1 = a & b;
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assign c = t1;
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endmodule
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