24 lines
464 B
Systemverilog
24 lines
464 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2021 Adrien Le Masle
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// SPDX-License-Identifier: CC0-1.0
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package pack_a;
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parameter PARAM_A = 0;
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endpackage : pack_a
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//module t;
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module t;
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parameter PARAM_A = 0;
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initial begin
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$display(PARAM_A);
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if (PARAM_A != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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