24 lines
462 B
Systemverilog
24 lines
462 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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o,
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// Inputs
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i
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);
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// Need some logic to get mtask debug fully covered
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input i;
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output wire o;
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assign o = i;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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