33 lines
706 B
Systemverilog
33 lines
706 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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initial begin
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begin : blk
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int x;
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fork : fork_blk
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begin
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#4;
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x = 3;
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end
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begin : begin_blk
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x = 1;
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#2;
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x = 2;
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end
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join_none
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#1;
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disable fork_blk.begin_blk;
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#2;
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if (x != 1) $stop;
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#2;
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if (x != 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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