20 lines
420 B
Systemverilog
20 lines
420 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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timeunit 10s; timeprecision 1s;
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initial begin
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#1;
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if ($time != 1) $stop;
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repeat (10) #1step;
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if ($time != 2) $stop;
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#10;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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