21 lines
490 B
Systemverilog
21 lines
490 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog 'alias'
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//
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// Simple bi-directional transitive alias test.
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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function int func();
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static int someVar = 12;
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return $cpure(someVar, "+ 6");
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endfunction
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module t;
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initial begin
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if (func() != 18) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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