16 lines
378 B
Systemverilog
16 lines
378 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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/* verilator lint_off COVERIGN */
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module t;
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covergroup cg0 with function sample ();
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endgroup
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cg0 cov = new();
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function void run();
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cov.sample();
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endfunction
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endmodule
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