14 lines
377 B
Verilog
14 lines
377 B
Verilog
// -*- Verilog -*-
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// lib.map file:
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include ./t_config_libmap/lib.map;
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library rtllib1 somepath -incdir somedir;
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library rtllib2 somewild*;
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library rtllib3 someexplicit;
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