21 lines
490 B
Verilog
21 lines
490 B
Verilog
// -*- Verilog -*-
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// lib.map file:
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library rtllib m?.v, m*.sv; // wildcard match (?, *)
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library rtllib2 sub/; // include directory match
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library rtllib5 m5.v; // explicit match
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// Note this does not start a comment
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library gatelib ./*.vg;
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// */
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config cfg;
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design t;
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endconfig
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