20 lines
372 B
Systemverilog
20 lines
372 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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m1 u_1();
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m2 u_2();
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m3 u_3();
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x4 u_4();
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m5 u_5();
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other u_o();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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