30 lines
575 B
Systemverilog
30 lines
575 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2022 Jomit626
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// SPDX-License-Identifier: CC0-1.0
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`ifndef WIDTH
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`define WIDTH 128
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`endif
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class item;
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bit [`WIDTH-1:0] data;
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endclass
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module t ();
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logic [`WIDTH-1:0] data;
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item item0 = new;
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initial begin
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item0.data = `WIDTH'hda7ada7a;
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data = item0.data;
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if (data != `WIDTH'hda7ada7a)
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$stop();
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$write("*-* All Finished *-*\n");
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$finish();
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end
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endmodule
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