30 lines
493 B
Systemverilog
30 lines
493 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module sub #(
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parameter type T = logic
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);
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mailbox #(T) mbox;
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endmodule
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module try #(
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parameter I = 1
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);
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endmodule
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module t;
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typedef struct packed {
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logic a;
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logic b;
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} my_struct_t;
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sub #(my_struct_t) u_sub ();
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try #(2) u_try2 ();
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initial $finish;
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endmodule
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