21 lines
381 B
Systemverilog
21 lines
381 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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class Base1;
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int memb1;
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endclass
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class Cls2 extends Base1;
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int memb2;
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endclass
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module t;
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initial begin
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Cls2 c;
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c.memb3 = 3; // Not found
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end
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endmodule
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