44 lines
868 B
Systemverilog
44 lines
868 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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int x;
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function new;
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x = 1;
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endfunction
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endclass
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class ExtendCls extends Cls;
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function new;
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x = 2;
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endfunction
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endclass
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class AnotherExtendCls extends Cls;
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function new;
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x = 3;
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endfunction
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endclass
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module t;
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initial begin
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automatic Cls cls = new;
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automatic ExtendCls ext_cls = new;
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automatic AnotherExtendCls an_ext_cls = new;
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if (cls.x == 1) cls = ext_cls;
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else cls = an_ext_cls;
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if (cls.x != 2) $stop;
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if (cls.x == 1) cls = ext_cls;
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else cls = an_ext_cls;
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if (cls.x != 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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