40 lines
599 B
Systemverilog
40 lines
599 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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endclass : Cls
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class Cls2;
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endclass
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class ClsExt extends Cls;
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endclass
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typedef Cls2 cls2_t;
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module t;
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Cls c;
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Cls2 c2;
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cls2_t ct2;
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ClsExt c_ext;
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task t(Cls c); endtask
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function void f(ClsExt c); endfunction
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initial begin
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c = 0;
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c = 1;
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c = c2;
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c_ext = c;
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ct2 = c;
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t(0);
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t(1);
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t(c2);
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f(c);
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end
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endmodule
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