20 lines
519 B
Systemverilog
20 lines
519 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input wire [31:0] foo,
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output reg [144:0] bar,
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output reg [144:0] bar2,
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output reg [144:0] bar3,
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output reg [144:0] bar4
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);
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// verilator lint_off SELRANGE
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assign bar[159:128] = foo;
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assign bar2[159] = foo[1];
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assign bar3[159-:32] = foo;
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assign bar4[128+:32] = foo;
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endmodule
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