21 lines
405 B
Systemverilog
21 lines
405 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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reg g;
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task automatic tsk;
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reg l;
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begin : cont_block
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assign g = signed'(l); // <--- BAD: using automatic in cont assignment
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end
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endtask
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initial $stop;
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endmodule
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